Xilinx Virtex-5 XC5VLX110T FPGA Two Xilinx XCF32P Platform Flash PROMs (32 Mbyte each) for storing large device configurations Xilinx SystemACE Compact Flash configuration controller 64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM) module compatible with EDK supported IP and software drivers On-board 32-bit ZBT synchronous SRAM and Intel P30 StrataFlash 10/100/1000 tri-speed Ethernet PHY supporting MII, GMII, RGMII, and SGMII interfaces USB host and peripheral controllers Programmable system clock generator Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks RS-232 port, 16x2 character LCD, and many other I/O devices and ports

The Virtex-5 OpenSPARC Evaluation Platform is a powerful system for hosting the OpenSparc T1 open-source microprocessor. Based on the Xilinx XUPV5-LX110T, a versatile general purpose development board powered by the Virtex¢ç-5 FPGA, this kit brings the throughput of OpenSPARC Chip Multi-Threading to an FPGA. Kit Includes: XUPV5-LX110T board 1GB Compact Flash card 256 MB SODIMM module SATA cable XUP USB-JTAG Programming Cable DVI to VGA adapter 6A power supply OpenSPARC T1 is the open-sourced version of the custom designed UltraSPARC T1 Microprocesor from Sun Microsystems. To broaden the appeal of this state-of-the-art Chip Multi-threading (CMT) technology to the developers, engineers at Sun Microsystems and Xilinx Inc. have developed a reference design that allows a scaled-down version of the OpenSPARC T1 processor to run on Xilinx Virtex 5 FPGAs. We believe this reference design will be an excellent starting point for researchers and entrepreneurs to build and test novel ideas in the areas of computer architecture, logic design, parallel programming, and compiler techniques, among others. For more details on how to download the OpenSPARC design and the reference design, please visit www.opensparc.net/fpga For documentation and reference designs, please visit http://www.xilinx.com/univ/xupv5-lx110t.htm For more information and to learn more about bringing Sun's OpenSPARC program to your university, please visit www.opensparc.net/edu/university-program.html

OpenSPARC on FPGA

OpenSPARC T1 release 1.6 now supports: T1 core supports single- and four-thread options on FPGAs Reference designs boot OpenSolaris on single- or four-thread mode Xilinx Virtex-5 technology support Networking (ftp, telnet) support These new features are designed to enable a user to build real systems using the OpenSPARC T1 core. If you are a professor you can apply for an OpenSPARC Evaluation Platform through our OpenSPARC University Program. One can also order OpenSPARC Evaluation Platform directly from Digilent. For pricing and ordering information, go to Digilent. Here is a video demonstrating OpenSPARC T1 running on the Xilinx Virtex 4 FPGA board. This presentation (updated for release 1.6 on July 3, 2008) is a Tutorial on using OpenSPARC T1 in an FPGA, "OpenSPARC T1 FPGA Implementation" Join the OpenSPARC FPGA project The FPGA Project intent is to allow FPGA implementation experts to take what was provided with the latest OpenSPARC T1 release and to further develop the FPGA implementation including work to optimize area and timing of this design and contribute their changes back to this project and to shared with the community. Contribute the project or just tell us what you have done. Initial join as an observer and with your contributions your role (and responsibility) will be increased. More Information Sun and Xilinx Unveil FPGA Board Update from RAMP Retreat, August 2008 - Shown is how two and four boards can be interconnected to build a multi-core OpenSPARC T1. Gaisler Research: GRLIB - The GRLIB IP Library is an integrated set of reusable IPcores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug & play method is used to configure and connect the IP cores without the need to modify any global resources.