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The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Standard development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.

DE10-Standard reviewed by 6 eminent scholars and experts!


Stephen A. Edwards Associate Professor of Computer Science, Columbia University	Peter Athanas Professor of ECE, Virginia Tech	Bill Nace Associate Teaching Professor of ECE, Carnegie Mellon University
Donald Bailey Professor of Imaging System, Massey University	Chris Burton Co-Founder of F&C Technologies	Anton Ruban Experienced YouTuber in FPGA Design

Click on the headshots to read the reviews!

Board Comparisons

Component Solution for Intel FPGAs


＊  Power Solution		＊ Memory Solution		＊ Clock Solution		＊ Ethernet Solution
＊  Inductive Component Solution		＊  Capacitive Component Solution		＊  ADC, Video, Accelerometer and Reset Generator Solution

The DE10-Standard board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.

The following hardware is provided on the board:

FPGA Device

• Cyclone V SX SoC—5CSXFC6D6F31C6N
• 110K LEs, 41509 ALMs
• 5,761 Kbits embedded memory
• 6 FPGA PLLs and 3 HPS PLLs
• 2 Hard Memory Controllers

ARM-Based Hard Processor System (HPS)

• 925 MHz, Dual-Core ARM Cortex-A9 MPCore Processor
• 512 KB of Shared L2 Cache
• 64 KB of Scratch RAM
• Multiport SDRAM Controller with Support for DDR2, DDR3, LPDDR1, and LPDDR2
• 8-Channel Direct Memory Access (DMA) Controller

Configuration and Debug

• Serial Configuration Device – EPCS128 on FPGA
• On-Board USB Blaster II (Normal Type B USB Connector)

Communication

• Two USB 2.0 Host Ports (ULPI Interface with USB Type A Connector) on HPS
• USB to UART (Micro USB Type B Connector) on HPS
• 10/100/1000 Ethernet on HPS
• PS/2 Mouse/Keyboard
• IR Emitter/Receiver

Connectors

• One 40-pin Expansion Header (Voltage Levels: 3.3V)
• One HSMC Connector(Configurable I/O Standards 1.5/1.8/2.5/3.3V)
• One 10-Pin ADC Input Header
• One LTC Connector (One Serial Peripheral Interface (SPI) Master ,One I2C and One GPIO Interface ) on HPS

Display

• 24-bit VGA DAC
• 128x64 Dots LCD Module with Backlight on HPS

Audio

• 24-bit CODEC, Line-in, Line-out, and Microphone-In Jacks

Video Input

• TV Decoder (NTSC/PAL/SECAM) and TV-In Connector

ADC

• Sample Rate: 500 KSPS
• Channel Number: 8
• Resolution: 12 bits
• Analog Input Range : 0 ~ 4.096 V

Switches, Buttons and Indicators

• 4 User Keys (FPGA x4)
• Channel Number: 8
• 10 User Switches (FPGA x10)
• 2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)7-Segment Display x6

Sensors

• G-Sensor on HPS

Power

• 12V DC Input

Block Diagram of the DE10-Standard Board

Connectivity




• Connect LT24




• Connect MTL2




• Connect D8M




• Connect D5M




• Connect SMK




• Connect RFS




• Connect HTG




• Connect ADA




• Connect DCC




• Connect LTC2607 (AD/DA Daugher Card)

• Size：166*130 mm

Documents



Title	Version	Size(KB)	Date Added	Download
DE10-Standard User Manual	1.0	11075	2017-03-09

CD-ROM



Title	Version	Size(KB)	Date Added	Download
DE10-Standard CD-ROM	1.1.1		2017-03-09
DE10-Standard SystemBuilder	1.0.0		2017-01-26
Quartus Download	16.1		2017-01-26

Daughtger Card Demonstrations



Title	Version	Size(KB)	Date Added	Download
ADA			2017-04-18
D5M			2017-04-18
D8M			2017-04-18
DCC			2017-04-18
LT24			2017-04-18
MTL2			2017-04-18
RFS			2017-04-18
SMK			2017-04-18

Linux BSP (Board Support Package): MicroSD Card Image



Title	Version	Size(KB)	Date Added	Download
Linux LXDE Desktop (Kernel 4.5)	1.1		2017-02-22
Linux Console (Kernel 4.5)	1.0		2017-01-26

BSP(Board Support Package) for Intel FPGA SDK OpenCL 16.1



Title	Version	Size(KB)	Date Added	Download
DE10-Standard OpenCL User Manual	1.0		2017-03-03
DE10-Standard OpenCL BSP(.zip)	1.0		2017-03-03
DE10-Standard OpenCL BSP(.tar.gz)	1.0		2017-03-03

Please note that all the source codes are provided "as-is". For further support or modification, please contact Terasic Support and your request will be transferred to Terasic Design Service. More resources about IP and Dev. Kit are available on Altera User Forums.

Demonstration


• FPGA
• My First FPGA
• Factory Default Code
• ADC Reading
• Audio Record and Play
• DRAM_RTL_Test
• DRAM_Nios_Test
• Karaoke Machine
• IR
• PS2 Mouse
• TV Box
• VIP Based TV Box
• SoC
• My First HPS
• GPIO Control
• G-sensor
• I2C Switch
• LCD
• SOC Advanced
• Audio Player Based on ALSA
• Bluetooth SPP
• Internet Time Query
• OpenCV
• Rough Line
• Camera In
• Face Detection
• SoC and FPGA
• Control FPGA LED from HPS
• Control Panel

Linux BSP


• Console BSP
• OpenCL BSP
• LXDE Desktop BSP
• Built-in QT and OpenCV Library
• GNU Tool chain for ARM
• Support USB Bluetooth, WiFi, and Camera Driver (See note below)
• ◦Support ALSA (Advanced Linux Sound Architecture) Driver

When you are shopping for accessories for the DE10-Standard, please be aware that not all USB dongles are compatible with this BSP. Here are some compatible USB dongles that have been tested, by us, and proven to work. The following suggested Bluetooth & WiFi USB dongles can be purchased from the Terasic Website.




• Bluetooth USB Dongle:
• Esens D704 (Terasic PN: FXX-3041-ESS)
• Wifi USB Dongle:
• ◦Mi WiFi (Terasic PN: FXX-3061-MIX)


The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Standard development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.

• Camera USB Dongle:
• Logitech C310
• ET USB 2760 Camera
• Genius WideCam F100

Control Panel

DE10-Standard Control Panel – allows users to access various components on the DE10-Standard platform from the LXDE Desktop BSP provided by Terasic. The relative project source codes are provided in the System CD for free.

System Builder

DE10-Standard System Builder – a powerful tool that comes with the DE10-Standard board. This tool allows users to create a Quartus project file on their custom design for the DE10-Standard board. The top-level design file, pin assignments, and I/O standard settings for the DE10-Standard board will be generated automatically from this tool. In addition, through the GPIO and HSMC connectors you can select various daughter cards in conjunction with the DE10-Standard using the DE10-Standard System Builder.

Other course resources you might interested: School: Cornell University Senior Lecturer: Bruce Land
Course 1: - ECE5760 Advanced Microcontroller Design and system-on-chip [DE2]
Course 2: - ECE 5760 Simplified Floating Point for DSP [DE2]

DE10-Standard Review

DE10-Standard Video Review. Conducted by Toni T800 (Mr. Anton Ruban)

Toni T800 (Mr. Ruban) has given Terasic the permission to publish his video review for DE10-Standard on Terasic's official youtube channel. )
Reviewed by Mr. Anton Ruban, Experienced FPGA Developer and Youtuber

1. DE10-Standard Board
2. DE10-Standard Quick Start Guide
3. Type A to B USB Cable
4. Type A to Mini-B USB Cable
5. Power DC Adapter (12V)
6. Four Silicon Footstands