• Xilinx XC6SLX100-2FGG676C or
  Xilinx XC6SLX150-2FGG676C
  

  Feature	XC6SLX100	XC6SLX150
  Slices	15,822	23,038
  Logic Cells	101,261	147,443
  Maximum Distributed RAM Bits	976	1,355
  Maximum user I/O pins(Device)	316	316
  Maximum user I/O pins(Board)	296	296
  Total Block RAM Bits	4,824	4,824
  DSP Slices	180	180

This table is for reference. Please refer to official data-sheets for certain information.

• 296 user I/O, 100 mil(2.54 mm) dual in-line.
• Separated VCCO input (VIO(B), VIO(D))
• On-board Oscillator, 30MHz and 50MHz
• External clock inputs through user I/O connector (CNA/CNB)
• DDR2 SDRAM(Micron: MT47H32M16HR-25E:G, 512Mbit)
  *1 Gbit/2 Gbit available : custom-order
• MRAM(Everspin: MR2A16AYS35, 4Mbit)
• Configuration device (Numonyx : M25P64)
• Four User Switches (push x2, slide x2)
• Eight User LEDs
• Two Status LEDs(Power, Done)
• Power-on Reset IC for FPGA configuration
• JTAG port(7 pin socket)
• JTAG buffer for stable download and debug
• 3.3 V single power supply operation with on-board 2,5 V/1.8 V/1.2V regulators
• High quality ten layers PCB.(Immersion gold)
• Controlled user I/O path length
  

  CNA	CNB	CNC	CND	On-board Termination for LVDS*	Board Revision:
  IOA0-63 MAX 43mm MIN 33mm	IOB0-31 MAX 31mm MIN 21mm IOB32-63 MAX 45mm MIN 35mm	IOC0-83 MAX 52mm MIN 42mm	IOD0-83 MAX 55mm MIN 45mm	16	A

  *LVDS standard is supported by limited I/Os.
• Credit-Card-Size 3.386"x 2.126" (86 x 54 mm)
• Tested all I/O
• RoHS compliance
• MADE IN JAPAN

Package Contents

Item	Image	Quantity
FPGA board(XCM-206-***)		1
Sockets(HIROSE 80pin)		2
Sockets(HIROSE 100pin)		2

There is no paper document such as user's manual and circuit schematic in the package.
Please download those documents from the link in the documentation section below.