▶ Overview

The FMC/FMC+ loopback card is designed for I/O testing of FPGA carried board equipped with the Vita57.1/57.4 standard FMC/FMC+ connector. These two cards can loopback most of the I/O of the FMC/FMC+ connector, including the group I/Os of HA, HB, LA, DP and clock. Users can use these two cards for high pin count (HPC) or low pin count (LPC) FMC/FMC+ connector. With these two cards, developers can quickly test the transmission speed of the high  or low speed FPGA I/O on the carrier board , and verify the I/O functionality.

In addition, the card also provides Ultra-Low Jitter Clock Multiplier, which can receive the clock output by the user from the carrier board, and then fan out to the clock pin (CLK_M2C_P/N and GBTCLK_M2C_P/N) of the FMC connector and transmit it back to the carrier board. Regarding the I2C interface on the FMC connector, the user can verify it by reading and writing the EEPROM on the loopback board via I2C interface.

▶ Specification

Block Diagram

• FMC Loopback Card

• FMC+ Loopback Card

Connection

• FMC Loopback Card with Terasic HAN board 
  
  
   
• FMC and FMC+ Loopback Card with Terasic Apollo S10 Board
  

▶ Resources

Documents

Please note that all the source codes are provided "as-is". For further support or modification, please contact Terasic Support and your request will be transferred to Terasic Design Service.

More resources about IP and Dev. Kit are available on Intel User Forums.